DDR??????????
RAS?? Row Address Strobe???е???????壻
CAS?? Column Address Strobe???е???????壻
tRCD?? RAS to CAS Delay??RAS??CAS????
CL?? CAS Latency??CAS?????????????????????CAS?????????????????????????????Σ?
RL?? Read Latency,?????????
tAC?? Access Time from CLK,?????????????????????I/O??????????????????????????????????????????I/O???????????????
tWR?? Write Recovery Time,д?????????????д???????????д??/У?????????????????????bank???????Ч?????????????????????????
BL?? Burst Lengths,???????????????????????????洢??????????????????????????????????漰???洢??????У??????????????????(SDRAM)????DDR SDRAM????????????????????
Precharge??L-Bank??????й????У?????????е??????
AL?? Additive Latency????????????DDR2????
WL?? Write Latency??д??????????????????????????????
tRAS: Active to Precharge Command??????Ч?????????????????
tDQSS?? WRITE Command to the first corresponding rising edge of DQS??DQS?????д?????????????
???Bank
SDRAM???????????洢???У????????????????洢???????????????row??,?????????У?Column??,????????о?????????????
о?λ??
SDRAM???о???δ????????????????о?λ???????????洢?????????????о???λ???????L-Bank??λ??????
?洢???????=????*????????????L-Bank??洢?????????*L-Bank???????????M*W???????о?????????M???о??д洢?????????????λ?????????дM????????1048576????W????????洢????????????????SDRAMо???λ??????λ??bit??
DDR SDRAM????洢?????????о?λ????о?I/O??λ???????????
DDR2 SDRAM????洢?????????о?λ?????????
DDR3 SDRAM????洢?????????о?λ????????
DDR4 SDRAM????洢?????????о?λ????????
????simon ?????????2019-08-30
